I. Field of the Disclosure
The technology of the disclosure relates generally to memory systems in computing devices and particularly to power saving techniques for memory systems.
II. Background
Computing devices have become common in current society. Mobile computing devices in particular have proliferated throughout many aspects of everyday life. Such mobile computing devices are powered by batteries that are periodically recharged. While advances in battery technology have increased the time that may pass before a battery needs to be recharged, such advances have been offset by the increasing functionality of mobile computing devices. That is, the additional functionality increases battery use, which in turn requires more frequent charging. Accordingly, pressure to decrease power consumption throughout the mobile computing device remains.
It should be appreciated that virtually all computing devices require memory elements of some sort to operate. While memory power consumption has been reduced by voltage scaling through successive iterations of low power double data rate (LPDDR) memory standards (e.g., LPDDR1 was set at 1.8 volts; LPDDR2 and LPDDR3 were set at 1.2 volts; and LPDDR4 was set at 1.1 volts), voltage scaling seems to have reached a plateau given current technology constraints. In particular, refresh limitations and other circuit performance issues necessitate the 1.1 volts of LPDDR4. The next generation of low-power memory (i.e., LPDDR5) is currently being debated, and LPDDR5 contemplates lowering the voltage to 1.05 volts, but this reduction offers only marginal power savings.
While power savings may be of particular interest in mobile computing devices, non-mobile devices may also benefit from reduced power consumption to reduce waste heat generation. Thus, computing devices of various sorts may benefit from memory systems that have decreased power consumption.